Microprocessors and Interfacing
Support Chips; 8085 vs 8086 Comparison
C-CAT
Support Chips
Intel designed support peripheral chips to extend microprocessor capabilities in minimum-mode systems:
| Chip | Name | Function |
|---|---|---|
| 8255 | Programmable Peripheral Interface (PPI) | 3 × 8-bit I/O ports (PA, PB, PC); modes 0, 1, 2; programmable direction |
| 8279 | Keyboard/Display Controller | Scanned keyboard and 7-segment display interface; FIFO buffer for key presses |
| 8253/8254 | Programmable Interval Timer (PIT) | Three independent 16-bit counters; generates precise time delays, baud rates, event counting |
| 8259 | Programmable Interrupt Controller (PIC) | Manages 8 levels of interrupts (8259 cascade → up to 64 levels); priority encoding, masking |
| 8251 | Programmable Communication Interface (USART) | Serial data communication; supports synchronous and asynchronous protocols; converts parallel ↔ serial |
30.1 8251 USART Modes
| Mode | Description |
|---|---|
| Synchronous | Sync characters transmitted; no start/stop bits per byte |
| Asynchronous | Start bit + data bits + optional parity + stop bit(s) |
30.2 Typical Minimum-Mode System
8086/8085 ──┬── 8255 (parallel I/O — switches, LEDs)
├── 8253 (timers — delays, scheduling)
├── 8259 (interrupt management)
├── 8279 (keyboard + display)
└── 8251 (serial comm — RS-232)
8085 vs 8086 Comparison
| Feature | Intel 8085 | Intel 8086 |
|---|---|---|
| Introduced | 1976 | 1978 |
| Technology | NMOS | HMOS |
| Data bus | 8-bit | 16-bit |
| Address bus | 16-bit | 20-bit |
| Addressable memory | 64 KB | 1 MB |
| Clock speed | 3 MHz (typical) | 5–10 MHz |
| Architecture | Single unit | BIU + EU (pipelined) |
| Prefetch queue | None | 6 bytes |
| Segmentation | No | Yes (CS, DS, SS, ES) |
| Physical address | Direct 16-bit | Seg × 10H + Offset |
| General registers | 6 × 8-bit + A | 8 × 16-bit (AX–DX) + pointers/index |
| Flags | 5 (S, Z, AC, P, CY) | 9 (adds OF, TF, IF, DF) |
| Hardware interrupts | 5 (TRAP, RST 7.5/6.5/5.5, INTR) | INTR, NMI |
| Software interrupts | RST 0–7 (8 vectors) | INT n (256 vectors, type 0–255) |
| Operating modes | Single | Minimum / Maximum |
| Pins | 40 | 40 (8086) / 8-bit external (8088) |
| Multiplier/Divider | No (software routines) | Hardware MUL/DIV (16-bit) |
| String instructions | No | Yes (MOVS, CMPS, etc.) |
| Stack growth | Downward | Downward |
| I/O addressing | Separate IN/OUT (256 ports) | IN/OUT + memory-mapped |
Programmable Support Devices
The 8255 Programmable Peripheral Interface supplies three programmable 8-bit ports. Mode 0 provides basic input or output. Mode 1 adds handshaking. Mode 2 gives Port A bidirectional bus operation. The control word selects modes and directions while bit set-reset mode changes individual Port C bits.
The 8253 and 8254 timers contain three independent counters used for delays, event counting, square-wave generation and baud-rate generation. The 8259 interrupt controller accepts several interrupt requests, prioritizes them and presents an interrupt to the processor. Cascading expands the number of sources. The 8251 USART converts parallel processor data to serial form and received serial data to parallel form. The 8279 scans a keyboard matrix, debounces keys and refreshes multiplexed displays.
Comparison of 8085 and 8086
The 8085 is an 8-bit processor with an 8-bit data bus and a 16-bit address bus, so it directly addresses 64 KiB. The 8086 has a 16-bit arithmetic unit and data bus with a 20-bit address bus, giving a 1 MiB physical address space. The 8086 forms a physical address by shifting a segment value four bits left and adding an offset.
The 8086 divides work between the Bus Interface Unit and Execution Unit. The BIU fetches instruction bytes into a six-byte queue while the EU executes instructions. This overlap provides simple pipelining. The 8086 also has more general registers, richer addressing modes, string instructions and minimum and maximum modes. The 8085 uses fixed hardware interrupt inputs. The 8086 uses a vector table containing 256 interrupt types.
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