Delay Calculation; 8086 Introduction; BIU and EU

Delay Calculation

21.1 Formula

Delay = (Number of T-states) × (Time period of one T-state)

Time period T = 1 / f

where f = clock frequency (Hz)

For 8085 at 3 MHz:

T = 1 / 3,000,000 = 0.333 μs per T-state

For 8085 at 2 MHz (standard example):

T = 1 / 2,000,000 = 0.5 μs per T-state

21.2 Counting T-States in a Delay Loop

MVI C, FFH ; 7 T-states (7T)
LOOP:
DCR C ; 4 T-states (4T) — except when C goes 01H→00H (7T for last iteration)
JNZ LOOP ; 10 T-states when taken (10T); 7T when not taken

Inner loop calculation (C counts 255 down to 0):

For C = 255 to 2: each iteration = 4T + 10T = 14T (253 iterations) For C = 1 → 0: 4T + 7T = 11T (1 iteration) Inner delay = (253 × 14) + 11 = 3542 + 11 = 3553 T-states

Detailed counting yields approximately 3567 T-states for the inner loop accounting for the final DCR behavior.

Inner loop delay at 2 MHz:

3567 × 0.5 μs = 1783.5 μs ≈ 1.784 ms

Outer loop (MVI C): 7T × 0.5 μs = 3.5 μs

Total delay ≈ 1.787 ms

21.3 General Delay Loop Formula

For a loop with counter initialized to N:

Total T-states ≈ (Outer instruction T) + N × (Loop body T per iteration) + correction for last pass

Always account for the extra T-states when the counter reaches zero (JNZ not taken = 7T instead of 10T).

8086 Introduction

The Intel 8086 is a 16-bit microprocessor introduced in 1978, using HMOS technology. It represents a major architectural leap from the 8085.

22.1 Key Specifications

Parameter	Value
Data bus	16-bit
Address bus	20-bit
Addressable memory	2²⁰ = 1,048,576 = 1 MB
Architecture	Segmented memory model
Internal organization	BIU + EU (pipelined)
Prefetch queue	6 bytes
Clock	5 MHz, 8 MHz, 10 MHz variants
Power	+5 V
Operating modes	Minimum mode (single processor), Maximum mode (multiprocessor)

BIU and EU

The 8086 is divided into two independent units that operate in parallel (pipelining):

┌─────────────────────────────────────────────────────────────┐
│ BUS INTERFACE UNIT (BIU) │
│ ┌──────────────┐ ┌─────────────┐ ┌──────────────────────┐ │
│ │ Segment │ │ Instruction│ │ Address Generation │ │
│ │ Registers │ │ Queue (6B) │ │ (Seg × 10H + Off) │ │
│ │ CS DS SS ES │ │ │ │ │ │
│ └──────────────┘ └─────────────┘ └──────────────────────┘ │
│ │ │ │ │
│ └────────────────┴──────────────────────┘ │
│ │ │
│ System Bus (20-bit addr, 16-bit data) │
└────────────────────────────┬────────────────────────────────────┘
 │ Internal Bus
┌────────────────────────────┴────────────────────────────────────┐
│ EXECUTION UNIT (EU) │
│ ┌──────────┐ ┌──────────────┐ ┌─────┐ ┌─────────────────┐ │
│ │ General │ │ Instruction │ │ ALU │ │ Flag Register │ │
│ │ Registers│ │ Decoder │ │ │ │ (9 flags) │ │
│ │ AX-DX etc│ │ │ │ │ │ │ │
│ └──────────┘ └──────────────┘ └─────┘ └─────────────────┘ │
└─────────────────────────────────────────────────────────────────┘

23.1 Bus Interface Unit (BIU)

Handles all bus operations: instruction fetch, memory read/write, I/O
Contains segment registers, instruction pointer (IP), 6-byte prefetch queue and address adder
EU has no direct connection to the system bus — all data/instruction traffic goes through BIU
While EU executes instruction N, BIU prefetches bytes for instructions N+1, N+2, … into the queue

23.2 Execution Unit (EU)

Decodes and executes instructions from the queue
Contains ALU, general-purpose registers, flag register and control circuitry
Tells BIU where to fetch/store data
Executes arithmetic, logic, branching and string operations

23.3 6-Byte Prefetch Queue and Pipelining

BIU prefetches up to 6 bytes of instruction stream ahead
When EU finishes current instruction, next byte(s) are already in queue — no wait for fetch
Overlapped fetch and execute = pipelining
Increases throughput dramatically vs non-pipelined 8085

Queue is flushed on branch (JMP, CALL, interrupt) — pipeline bubble