Addressing Modes; Instruction Cycle, Machine Cycle and T-State

Addressing Modes

The addressing mode specifies how the operand of an instruction is located.

11.1 Immediate Addressing Mode

Operand is embedded in the instruction itself
No separate memory fetch for operand (except the instruction bytes)
Fastest mode — operand available immediately after fetch

MVI B, 20H ; 20H copied directly into register B
ADI 72H ; 72H added immediately to accumulator
LXI H, 2050H ; 16-bit immediate 2050H loaded into HL pair

11.2 Register Addressing Mode

Operand is in a CPU register
Data transferred or operated between registers

MOV A, B ; Copy B into A (B unchanged)
ADD C ; Add register C to accumulator
XRA D ; XOR accumulator with D

11.3 Register Indirect Addressing Mode

Register pair holds a memory address; data is in memory at that address
Uses HL, BC or DE pairs
M in instruction means "memory location pointed by HL"

MOV A, M ; A ← Memory[HL]
LDAX B ; A ← Memory[BC]
STAX D ; Memory[DE] ← A

Example: If HL = 2006H and memory[2006H] = 3AH, then MOV A, M loads 3AH into A.

11.4 Direct Addressing Mode

16-bit address specified directly in the instruction
Single memory reference to access operand

LDA 2050H ; A ← Memory[2050H]
STA 3050H ; Memory[3050H] ← A
JMP 4000H ; Unconditional jump to 4000H

11.5 Implied (Implicit) Addressing Mode

No explicit operand — operation is inherent in opcode
Data location is implied

CMA ; Complement accumulator (A is implied)
RAR ; Rotate A right through carry
HLT ; Halt processor
CMP B ; Compare — A and B implied

11.6 Addressing Mode Summary Table

Mode	Operand location	Example
Immediate	In instruction	MVI A, 50H
Register	CPU register	MOV B, A
Register indirect	Memory at [HL/BC/DE]	MOV A, M
Direct	Memory at 16-bit address	LDA 3000H
Implied	Implicit in opcode	CMA, HLT

Instruction Cycle, Machine Cycle and T-State

12.1 Definitions

Term	Definition
T-State	One clock period — the smallest time unit; basic timing measure
Machine Cycle	Time to complete one bus operation (fetch, memory read, memory write, I/O) — consists of 3 to 6 T-states
Instruction Cycle	Time to fetch and execute one complete instruction — one or more machine cycles

Instruction Cycle
├── Machine Cycle 1 (Opcode Fetch) — 4 T-states
├── Machine Cycle 2 (Memory Read) — 3 T-states (if needed)
├── Machine Cycle 3 (Memory Write) — 3 T-states (if needed)
└── ...

12.2 Standard Machine Cycle Durations

Machine cycle	T-states	Description
Opcode fetch	4T	Fetch instruction byte from memory
Memory read	3T	Read data from memory
Memory write	3T	Write data to memory
I/O read	3T	Read from I/O port
I/O write	3T	Write to I/O port

12.3 Instruction Word Sizes

Size	Bytes	Example	Typical T-states
1-byte	1	MOV A, B; ADD C; HLT	4T (fetch only) to 7T
2-byte	2	MVI A, 3EH; ADI 72H	7T (4+3)
3-byte	3	LDA 2050H; JMP addr	10T–13T (4+3+3 or more)

12.4 Worked Timing Examples

MVI A, 3EH (2-byte instruction):

MC1: Opcode fetch = 4T
MC2: Read immediate operand (3EH) = 3T
Total = 7T

LDA 2050H (3-byte instruction):

MC1: Opcode fetch = 4T
MC2: Read address low/high = 3T
MC3: Read data from 2050H = 3T
Total = 10T (some references cite 13T depending on exact cycle counting)

At 3 MHz: T-state = 1/3 MHz ≈ 0.333 μs 7T instruction ≈ 7 × 0.333 μs ≈ 2.33 μs