8085 Pin Diagram; Control and Status Signals; Interrupts in 8085

8085 Pin Diagram

The 8085 is a 40-pin IC operating on +5 V at 3 MHz. Pins are grouped into six functional categories:

8.1 Pin Groups

Group	Pins	Function
Address bus	A8–A15, AD0–AD7 (multiplexed)	16-bit address
Data bus	AD0–AD7 (shared with address low)	8-bit data
Control & status	ALE, RD', WR', IO/M', S1, S0	Bus control
Power & clock	VCC (+5V), VSS (GND), X1, X2, CLK OUT	Power and crystal oscillator
Externally initiated	TRAP, RST 7.5, RST 6.5, RST 5.5, INTR, INTA', RESET IN, RESET OUT, READY, HOLD, HLDA	Interrupts, reset, DMA, wait
Serial I/O	SID, SOD	Serial input/output data

8.2 Multiplexed Address/Data Lines (AD0–AD7)

During T1 of a machine cycle, AD0–AD7 carry the lower 8 address bits. ALE goes HIGH → external latch (e.g., 74LS373) captures the address. When ALE goes LOW, the same pins carry data. This multiplexing saves pins — without it, a separate 8-bit data bus plus 16-bit address would need more pins.

8.3 Clock Pins

X1, X2: Crystal connections (typically 6 MHz crystal; internally divided by 2 → 3 MHz operating frequency)
CLK OUT: Clock output for peripheral synchronization

Control and Status Signals

9.1 RD' (Read)

Active LOW
Indicates CPU wants to read from memory or I/O
Data must be valid on the bus when RD' is asserted

9.2 WR' (Write)

Active LOW
Indicates CPU will write data to memory or I/O
Data is placed on bus by CPU during WR'

9.3 ALE (Address Latch Enable)

Positive pulse at start of each machine cycle
ALE = 1 (HIGH): Address is present on AD0–AD7 — latch it
ALE = 0 (LOW): Data phase — AD0–AD7 carry data

9.4 IO/M' (Input-Output / Memory)

IO/M' = 1 (HIGH): Current operation is I/O
IO/M' = 0 (LOW): Current operation is Memory
Combined with RD'/WR' to fully decode bus cycle type

9.5 S0 and S1 (Status)

Identify the type of machine cycle in progress
Used with IO/M' by external decoding logic to generate chip selects

Interrupts in 8085

An interrupt is a signal from an external device (or software instruction) that temporarily suspends the current program, saves return address on stack and branches to an Interrupt Service Routine (ISR).

10.1 Five Hardware Interrupts

Interrupt	Type	Maskable?	Vector address	Priority
TRAP	Hardware	Non-maskable	0024H	Highest (1)
RST 7.5	Hardware	Maskable	003CH	2
RST 6.5	Hardware	Maskable	0034H	3
RST 5.5	Hardware	Maskable	002CH	4
INTR	Hardware	Maskable	Supplied externally	Lowest (5)

10.2 Vector vs Non-Vector Interrupts

Type	Address known?	Examples
Vectored	Yes — fixed ISR address	TRAP, RST 7.5, RST 6.5, RST 5.5
Non-vectored	No — device sends address during INTA cycle	INTR

10.3 Eight Software Interrupts (RST 0 – RST 7)

Software interrupts are invoked by RST n instructions (one-byte opcodes):

Instruction	Vector address	Hex offset
RST 0	0000H	0 × 8
RST 1	0008H	1 × 8
RST 2	0010H	2 × 8
RST 3	0018H	3 × 8
RST 4	0020H	4 × 8
RST 5	0028H	5 × 8
RST 6	0030H	6 × 8
RST 7	0038H	7 × 8

Pattern: Vector address = n × 8 (in hex: n × 08H)

10.4 Interrupt Processing Steps

Current PC is pushed onto the stack
PC is loaded with vector address

ISR executes at that address 4. RET (or RTI equivalent) pops return address and resumes main program

10.5 Interrupt Control Instructions

Instruction	Function
EI (Enable Interrupts)	Sets interrupt enable flip-flop; allows maskable interrupts
DI (Disable Interrupts)	Resets interrupt enable; blocks maskable interrupts
RIM (Read Interrupt Mask)	Reads interrupt mask status and serial input (SID)
SIM (Set Interrupt Mask)	Masks/unmasks RST 7.5/6.5/5.5; controls SOD serial output

10.6 TRAP — Special Properties

Non-maskable — cannot be disabled by DI
Edge and level triggered
Highest priority — used for catastrophic events (power failure backup, critical fault)
Jumps to 0024H