ALU, Instruction Register and Decoder; Timing and Control Unit; Three Buses

ALU, Instruction Register and Decoder

5.1 Arithmetic Logic Unit (ALU)

The ALU performs all 8-bit arithmetic and logical operations:

Type	Operations
Arithmetic	Addition, subtraction, increment, decrement, compare
Logical	AND OR, XOR, NOT (complement)
Shift/Rotate	Left/right shifts and rotates through carry

The ALU takes operands from the accumulator and either a register, immediate data or memory (via internal bus), computes the result, stores it back in A and updates the flag register.

5.2 Instruction Register (IR)

Holds the opcode (operation code) of the instruction currently being executed
After fetch, the opcode byte from memory resides in IR
Connected to the instruction decoder

5.3 Instruction Decoder

Decodes the bit pattern in IR to generate specific control signals
Tells the timing unit which machine cycles to execute (fetch, memory read, I/O write, etc.)

Determines which registers participate and whether flags should be updated

Timing and Control Unit

The Timing and Control Unit generates all synchronization and bus control signals required for internal and external operation.

6.1 Control Signals (to external world)

Signal	Description
ALE	Address Latch Enable — HIGH during address phase of multiplexed bus
RD'	Read strobe — active LOW; memory/I/O read
WR'	Write strobe — active LOW; memory/I/O write

6.2 Status Signals

Signal	Description
IO/M'	HIGH = I/O operation; LOW = memory operation
S1, S0	Encode current machine cycle type (opcode fetch, read, write, halt)

6.3 S1/S0 Encoding (Status)

IO/M'	S1	S0	Cycle type
0	1	1	Opcode fetch
0	1	0	Memory read
0	0	1	Memory write
1	1	0	I/O read
1	0	1	I/O write
1	0	0	Halt

6.4 Other Control Signals

Signal	Purpose
HOLD / HLDA	DMA bus request and acknowledge
READY	Wait-state control — if LOW, CPU inserts wait states
RESET IN / RESET OUT	System reset
INTA'	Interrupt acknowledge

Three Buses

The 8085 communicates with memory and I/O through three buses:

7.1 Address Bus (16-bit, Unidirectional)

Carries memory or I/O addresses from CPU to memory/I/O devices
16 lines → 64 KB address space
Higher order: A8–A15 (dedicated pins)
Lower order: A0–A7 multiplexed with data on AD0–AD7
Direction: CPU → Memory/I/O only (unidirectional)

7.2 Data Bus (8-bit, Bidirectional)

Carries data between CPU and memory/I/O
8 lines (D0–D7 or AD0–AD7 when demultiplexed)
Bidirectional: Read loads data into CPU; write sends data out
Maximum unsigned value per transfer: 255 (FFH)

7.3 Control Bus (Mixed Direction)

Collection of control and status lines
Partly unidirectional (RD', WR', ALE from CPU) and partly bidirectional (HOLD/HLDA, READY, interrupt lines)
Coordinates when and what type of transfer occurs

 ┌─────────┐
 │ 8085 │
 │ CPU │
 └──┬──┬──┬─┘
 Address│ │ │Control
 (16) │ │ │(RD,WR,ALE,IO/M,S0,S1,...)
 │ │
 │ └── Data (8, bidirectional)
 │
 ▼
 ┌──────────────┐
 │ Memory / I/O │
 └──────────────┘