8085 Introduction and Specifications; 8085 Architecture Overview

8085 Introduction and Specifications

The Intel 8085 (pronounced "eighty-eighty-five") is an 8-bit microprocessor introduced by Intel in 1976 using NMOS technology. It is an enhanced successor to the 8080 and became the workhorse of early microcomputer education and embedded design in India and worldwide.

1.1 Key Specifications

Parameter	Value	Notes
Data bus	8-bit	Transfers one byte per bus cycle; 2⁸ = 256 distinct byte values (00H–FFH)
Address bus	16-bit	Can address 2¹⁶ = 65,536 = 64 KB of memory
Architecture	Single-chip CPU	Von Neumann — program and data share same address space
Technology	NMOS	N-channel MOS; predecessor to HMOS in 8086
Clock frequency	3 MHz (typical)	Single-phase clock; some variants run at 5 MHz
Power supply	+5 V	VCC and VSS (ground)
Package	40-pin DIP	Dual In-line Package
Program Counter	16-bit	Points to next instruction address
Stack Pointer	16-bit	Points to top of stack in memory
General-purpose registers	Six 8-bit (B, C, D, E, H, L)	Usable as three 16-bit pairs: BC, DE, HL
Interrupt inputs	5 hardware + 8 software	TRAP, RST 7.5, RST 6.5, RST 5.5, INTR

1.2 Why 64 KB?

With a 16-bit address bus, the processor can generate addresses from 0000H to FFFFH:

2^16 = 65,536 locations × 1 byte/location = 64 KB

This is the maximum directly addressable memory without banking or paging extensions.

1.3 Position in Intel Timeline

Year	Processor	Data / Address	Key Feature
1971	4004	4-bit	First commercial microprocessor
1972	8008	8-bit

| 1974 | 8080 | 8-bit / 16-bit addr | | |

| 1976 | 8085 | 8-bit / 16-bit addr | +5 V, on-chip clock, extra interrupts | | 1978 | 8086 | 16-bit / 20-bit addr | 1 MB, pipelining, segmentation |

8085 Architecture Overview

The internal architecture of the 8085 can be visualized as a datapath connecting registers, ALU and control logic through an 8-bit internal data bus, with a 16-bit address path for memory access.

 ┌─────────────────────────────────────────────┐
 │ TIMING & CONTROL UNIT │
 │ (generates RD', WR', ALE, S0, S1, etc.) │
 └──────────────────────┬──────────────────────┘
 │
 ┌──────────┐ ┌──────────┐ ┌─────────▼─────────┐ ┌──────────┐
 │ B C │ │ D E │ │ ACCUMULATOR │ │ Flags │
 │ (BC) │ │ (DE) │ │ (A) │ │ S Z AC P C│
 └────┬─────┘ └────┬─────┘ └─────────┬─────────┘ └────┬─────┘
 │ │ │ │
 ┌────┴─────┐ ┌────┴─────┐ │ ┌─────┴─────┐
 │ H L │ │ W Z │ │ │ IR │
 │ (HL) │ │ (temp) │ │ │ + Decoder │
 └────┬─────┘ └────┬─────┘ │ └─────┬─────┘
 │ │ │ │
 └─────────────┴───────────────────┼───────────────────┘
 │
 ┌────────────▼────────────┐
 │ 8-bit INTERNAL BUS │
 └────────────┬────────────┘
 │
 ┌────────────▼────────────┐
 │ ALU │
 │ (Add, Sub AND OR, │
 │ XOR, Compare, Shift) │
 └────────────┬────────────┘
 │
 ┌─────────────────────────────────┼─────────────────────────┐
 │ │ │
 ┌────▼─────┐ ┌──────▼──────┐ ┌──────▼──────┐
 │ PC │ │ SP │ │ ADDRESS │
 │ (16-bit) │ │ (16-bit) │ │ BUFFER │
 └────┬─────┘ └──────┬──────┘ └──────┬──────┘
 │ │ │
 └─────────────────────────────────┴─────────────────────────┘
 │
 ┌──────────────────────┴──────────────────────┐
 │ EXTERNAL: Address Bus (16) + Data Bus (8) │
 │ + Control Bus │
 └─────────────────────────────────────────────┘

2.1 Functional Blocks

Block	Function
Register array	Holds operands, addresses and stack pointer
ALU	Performs arithmetic and logic on 8-bit data
Accumulator (A)	Primary operand/result register for ALU ops
Flag register	Stores condition codes after ALU operations
Instruction Register (IR)	Holds current opcode being decoded
Instruction Decoder	Translates opcode into control signals
Timing & Control	Generates bus signals synchronized to clock
Address buffer	Drives A8–A15 and multiplexed AD0–AD7
PC / SP	Sequencing (program flow) and stack management