Ripple Counter vs Synchronous Counter and Hazards in Combinational Circuits

Ripple Counter vs Synchronous Counter

25.1 Asynchronous (Ripple) Counter

FF output clocks next FF
Propagation delay accumulates — slow for large n
Simple wiring

CLK → FF0 → FF1 → FF2 → FF3
 Q0 Q1 Q2 Q3

25.2 Synchronous Counter

Same clock to all FFs
Logic generates next state from present state
Faster, predictable timing
Used in CPUs and high-speed systems

25.3 Mod-10 Decade Counter

Counts 0000 → 1001 → reset to 0000.

Requires feedback to reset when count reaches 1010.

Ring Counter and Johnson Counter

26.1 Ring Counter (Circulating Register)

N FFs connected in ring — one hot state circulates.

Clock	Q3	Q2	Q1	Q0
0	1	0	0	0
1	0	1	0	0
2	0	0	1	0
3	0	0	0	1

Modulus = n (number of FFs)

26.2 Johnson Counter (Twisted Ring)

Inverted output fed back to input.

Sequence for 4 FFs: 0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000

Modulus = 2n

Excitation Tables — Design Procedure

To design sequential circuit from state diagram:

Draw state table (present state, input, next state, output)
Convert next state to excitation inputs using flip-flop excitation table
Derive K-maps for each excitation variable
Minimize and implement

JK Excitation Table

Qn	Q(n+1)	J	K
0	0	0	X
0	1	1	X
1	0	X	1
1	1	X	0

D Excitation Table

Qn	Q(n+1)	D
0	0	0
0	1	1
1	0	0
1	1	1

D = Q(n+1) — simplest design

Hazards in Combinational Circuits

28.1 Static-1 Hazard

Output should stay 1 but briefly glitches to 0 due to path delay differences.

Fix: Add redundant term (consensus term) to cover transition.

28.2 Static-0 Hazard

Brief 1 pulse when output should stay 0.

28.3 Dynamic Hazard

Multiple transitions on single input change — rare in well-designed circuits.