MUX Implementation and Boolean Expressions; Decoder as Logic Generator; Priority Encoder

MUX Implementation and Boolean Expressions

22.1 Implementing Functions with MUX

Any n-variable function can be implemented with a 2^(n-1)-to-1 MUX by connecting constants 0/1 to data inputs.

Example: Implement F(A,B,C) using 4:1 MUX:

• Use A,B as select lines
• Connect C or C' to data inputs based on truth table

22.2 MUX as Universal Logic

A 4:1 MUX can implement any 3-variable function — useful in FPGA-style design thinking.

Decoder as Logic Generator

A n-to-2ⁿ decoder with AND gates on outputs implements any n-variable function.

Example: Full adder using decoders:

• 3-to-8 decoder for inputs A, B, Cin
• OR together outputs for Sum and Cout minterms

Priority Encoder

When multiple inputs are active, priority encoder outputs code of highest priority input.

I3 has highest priority.

Implementing Logic with a Multiplexer

A multiplexer can implement a Boolean function by using some variables as select inputs and connecting each data input to 0, 1, a remaining variable or its complement. For a three-variable function implemented with a 4-to-1 multiplexer, two variables select one of four inputs. The function is evaluated for each select combination as the third variable changes. The resulting pair of values determines whether that data input is 0, 1, C or C̅.

An 8-to-1 multiplexer can implement any function of three variables directly. Connect the variables to the select lines and place the function’s truth-table output on each data input. Larger functions can use a larger multiplexer or a hierarchy of smaller devices. Enable inputs must be placed at their active level; an active-low enable disables the device when driven high.

Decoders and Priority Encoders

A decoder activates one output for each binary input combination. An n-to-2^n decoder therefore generates all minterms of n variables. ORing the outputs associated with a function’s minterm numbers implements the function. Active-low decoder outputs require NAND or inverted logic according to the device truth table.

An ordinary encoder assumes that only one input is active. A priority encoder remains defined when several inputs are active by selecting the highest-priority input. Besides the encoded output it commonly provides a valid signal indicating that at least one input is active. Cascading inputs and outputs allow several encoders to represent a larger input set.