Digital Electronics
Sequential Logic Circuits; Flip-Flops; Shift Registers
C-CAT
Sequential Logic Circuits
Definition: Output depends on present input AND past outputs (has memory).
14.1 Types
| Type | Clock | Speed | Design |
|---|---|---|---|
| Asynchronous | No global clock; input pulses | Faster | Harder |
| Synchronous | Global clock | Slower | Easier |
14.2 Latch vs Flip-Flop
| --- | | Latch | Flip-Flop | | --- | --- | --- | | Clock | Level-sensitive | Edge-sensitive | | Output change | Any time (enabled) | Only on clock edge | | Type | Unclocked | Clocked |
14.3 Triggering Types
- Positive level: Output changes during HIGH clock
- Negative level: Output changes during LOW clock
- Positive edge: Changes on rising edge ↑
- Negative edge: Changes on falling edge ↓
14.4 Timing Parameters
| Parameter | Meaning |
|---|---|
| Setup time (tsu) | Data must be stable BEFORE clock edge |
| Hold time (th) | Data must remain stable AFTER clock edge |
| Propagation delay (tp) | Time from input change to output change |
Flip-Flops
15.1 SR Flip-Flop
| CLK | S | R | Q(n+1) | State |
|---|---|---|---|---|
| ↑ | 0 | 0 | Qn | No change |
| ↑ | 0 | 1 | 0 | Reset |
| ↑ | 1 | 0 | 1 | Set |
| ↑ | 1 | 1 | ? | Invalid (race) |
Application: Switch debouncing Problem: S=R=1 is forbidden
15.2 D Flip-Flop (Delay / Data)
- D input connected to S; D̄ to R
- Q(n+1) = D — follows input
Applications: Data registers, shift registers, frequency dividers
| CLK | D | Q(n+1) |
|---|---|---|
| ↑ | 0 | 0 |
| ↑ | 1 | 1 |
15.3 JK Flip-Flop
| CLK | J | K | Q(n+1) |
|---|---|---|---|
| ↑ | 0 | 0 | Qn |
| ↑ | 0 | 1 | 0 |
| ↑ | 1 | 0 | 1 |
| ↑ | 1 | 1 | Q̄n (toggle) |
Characteristic equation: Q(n+1) = JQ' + K'Q
Applications: Counters, shift registers, frequency division
Race-around: When J=K=1 and clock is HIGH too long — solved by Master-Slave JK
15.4 T Flip-Flop (Toggle)
| CLK | T | Q(n+1) |
|---|---|---|
| ↑ | 0 | Qn |
| ↑ | 1 | Q̄n |
Application: Frequency division (divide by 2)
15.5 Master-Slave JK
- Two JK FFs in series
- Master: active on clock HIGH
- Slave: active on clock LOW
Eliminates race-around condition
Shift Registers
A register = group of flip-flops storing n bits.
16.1 Types
| Type | Input | Output | Abbreviation |
|---|---|---|---|
| Serial In Serial Out | 1 bit serial | 1 bit serial | SISO |
| Serial In Parallel Out | 1 bit serial | n bits parallel | SIPO |
| Parallel In Serial Out | n bits parallel | 1 bit serial | PISO |
| Parallel In Parallel Out | n bits parallel | n bits parallel | PIPO |
16.2 Shift Directions
- Shift right: Input from right, bits move left
- Shift left: Input from left, bits move right
- Bidirectional: Controlled by direction signal
16.3 SISO Operation Example
Load serial data 1001 (MSB first) into 4-bit register:
| Clock | Register Content |
|---|---|
| Initial | 0000 |
| 1st ↑ | 1000 |
| 2nd ↑ | 0100 |
| 3rd ↑ | 0010 |
| 4th ↑ | 1001 |
16.4 Applications
- Temporary data storage
- Delay elements
- Serial communication
- Universal shift register (bidirectional + parallel load)
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