Pipelining Tradeoffs; Interleaved Memory; Intel Processor Evolution

Pipelining Tradeoffs

22.1 Advantages

Advantage	Explanation
Reduced effective cycle time	More instructions complete per wall-clock second
Higher throughput	Pipeline keeps ALU and fetch busy
Better resource utilization	While one stage runs IE, another can IF

22.2 Disadvantages

Disadvantage	Explanation
Complex design	Hazards, forwarding, branch prediction
Higher cost	More registers, control logic
Not always faster for one instruction	Latency ≥ non-pipeline for single inst

Interleaved Memory

Interleaved memory splits main memory into banks accessed in parallel to reduce wait states.

23.1 4-Way Interleaving

Four banks, each 256 bytes (example):

Block-oriented (no interleaving):

Addresses 0–255 → Bank 0
256–511 → Bank 1
etc.

Interleaved:

Address 0 → Bank 0
Address 1 → Bank 1
Address 2 → Bank 2
Address 3 → Bank 3

Address 4 → Bank 0 again

CPU can access alternate banks without waiting for a single monolithic bank to finish.

23.2 Even/Odd Bank Scheme

Two physical banks of n words:

Even addresses → physical bank 0
Odd addresses → physical bank 1

Allows concurrent access patterns in some designs.

23.3 Benefits

Increases effective memory bandwidth
Makes system faster and more efficient when combined with cache and pipelining

Intel Processor Evolution

Year	Chip	Data / Address	Technology	Key notes
1971	4004	4-bit	PMOS	First commercial microprocessor
1972	8008	8-bit	PMOS

| 1974 | 8080 | 8-bit | NMOS | Sign-magnitude era; popular in kits | | 1976 | 8085 | 8-bit / 16-bit addr | NMOS, 3 MHz, +5 V | 64 KB space; enhanced 8080 | | 1978 | 8086 | 16-bit / 20-bit addr | HMOS | 1 MB, pipelining, BIU/EU | | 1982 | 80286 | 16-bit / 24-bit | | Protected mode | | 1985 | 80386 | 32-bit | | CISC, virtual memory | | 1989 | 80486 | 32-bit | | Integrated FPU, cache | | 1993 | Pentium | 32-bit (64-bit data path) | | Superscalar, not "80586" marketing name |

8085 highlights: 8-bit data bus, 16-bit address → 2¹⁶ = 64 KB, NMOS, single-phase clock, +5 V. 8086 highlights: 16-bit data, 20-bit address → 2²⁰ = 1 MB, 6-byte prefetch queue, segmented addressing.

Interleaving and Pipeline Tradeoffs

Interleaved memory divides addresses among banks so consecutive requests can overlap when they reach different banks. Low-order interleaving commonly chooses a bank from low address bits and a word within the bank from higher bits. With m banks, sequential words rotate through the banks. Repeated addresses mapping to one busy bank create conflicts and remove the benefit.

Pipelining raises throughput but adds registers, control and power. Unequal stage delays force faster stages to wait for the slowest one. Deep pipelines may support high clock rates but increase branch penalties and forwarding complexity. Superscalar processors issue several instructions in one cycle when dependencies and resources allow it. Out-of-order execution searches for ready instructions while retirement preserves architectural correctness.

Processor Evolution

Early microprocessors integrated a small arithmetic unit and register set with external memory and peripherals. Wider data paths and address buses increased precision and address space. Later processors introduced caches, protected memory, floating-point hardware and deeper pipelines. Superscalar execution, branch prediction and out-of-order scheduling increased instruction-level parallelism.

Modern designs use several cores because frequency and power cannot scale without limit. Vector and SIMD instructions apply one operation to several data elements. Simultaneous multithreading exposes more than one instruction stream to a core. Architectural compatibility may preserve an old instruction set while internal execution uses decoded micro-operations and modern pipelines.