DMA; Interrupts; Non-Pipelined Execution

DMA

Direct Memory Access (DMA) lets a peripheral device transfer data to/from memory without the CPU executing every byte transfer.

16.1 Why DMA?

Programmed I/O wastes CPU cycles copying disk/network buffers. DMA removes the CPU from the datapath for bulk transfers.

16.2 DMA Controller

• Manages bus cycles on memory bus.
• CPU sets up source, destination, count; DMA chip arbitrates.
• On completion, DMA may interrupt the CPU.

16.3 Applications

• Disk controllers, graphics cards, network cards, sound cards
• Intra-chip DMA in multicore SoCs

 CPU sets up ──▶ [DMA Controller] ◀──▶ Memory
 ▲
 │
 Peripheral (disk)

Interrupts

An interrupt is a signal that stops normal program flow so the CPU services an urgent event.

17.1 Basic Flow

1. Device asserts interrupt when ready.
2. CPU finishes current instruction (usually).

CPU saves context, jumps to ISR (Interrupt Service Routine). 4. After ISR, return to interrupted program.

17.2 Priority Interrupt

When multiple devices interrupt together, priority decides order:

• High priority: magnetic disk, high-speed I/O
• Low priority: keyboard

CPU services highest priority first.

17.3 Hardware vs Software

17.4 Maskable vs Non-Maskable

17.5 Software Interrupt Subtypes

• Normal software interrupt: deliberate INT / SWI for OS services.
• Exception: unplanned (divide by zero, page fault).

Non-Pipelined Execution

In non-pipelined architecture:

• Instructions execute strictly one after another.
• Instruction n+1 starts only after instruction n fully completes all stages.
• Highly simple but inefficient — functional units idle during stages they don't need.

18.1 Timing Model

If each instruction needs K stages and each stage takes one clock (for simplicity):

[ \text{Total cycles for } N \text{ instructions} = K \times N ]

Standard notation:

• K = number of stages (e.g. Fetch, Decode, Execute → K=3)
• N = number of instructions

18.2 Example (K=4, N=5)

Stages: IF, ID, IE, WB (four stages).

[ \text{Cycles} = K \times N = 4 \times 5 = 20 ]

18.3 Example (K=3, t=0.25 s per stage, N=3)

Sequential F-D-E for three instructions:

[ \text{Time} = N \times K \times t = 3 \times 3 \times 0.25 = 0.75 \text{ s} ]

DMA Operation and Interrupts

A DMA controller receives a starting address, transfer count and direction from the processor. It then requests control of the bus, transfers data between the device and memory and updates its address and count. Burst mode holds the bus for a block. Cycle stealing takes individual bus cycles. Transparent DMA attempts transfers when the processor is not using the bus. Completion or error normally raises an interrupt.

An interrupt causes the processor to finish or suspend its current instruction according to the architecture, save return state and branch to a service routine. Maskable interrupts can be disabled for controlled critical periods. Non-maskable interrupts serve urgent conditions. Vectored interrupts supply or imply a service address. Priority logic chooses among simultaneous requests. The return-from-interrupt instruction restores saved state and resumes the interrupted program.

Non-Pipelined Datapath

In non-pipelined execution one instruction completes its required stages before the next instruction begins. A multicycle processor may reuse one arithmetic unit across fetch, effective-address calculation and execution. Control selects register transfers for each clock step. The clock period can match the slowest step rather than the complete instruction, but instructions do not overlap.

Latency is the time for one instruction while throughput is completed instructions per unit time. Non-pipelined control is easier to design and has no pipeline hazards. Its throughput is lower because units that are unused during a step cannot automatically work on another instruction.