Word, Byte and Capacity; Von Neumann vs Harvard; CISC vs RISC

Word, Byte and Capacity

13.1 Bit Groupings

Name	Size	Notes
Bit	1 binary digit	0 or 1
Nibble	4 bits	One hex digit
Byte	8 bits	Standard addressable unit in many systems
Word	CPU-dependent (16, 32, 64 bits)	"Natural" operand size

A memory word is a group of bits stored together — may represent a number, opcode or characters.

13.2 Binary Prefixes (Computer Science)

Symbol	Value	Power
K (Kilo)	1024	2¹⁰
M (Mega)	1024 K	2²⁰
G (Giga)	1024 M	2³⁰
T (Tera)	1024 G	2⁴⁰

Example conversions:

1 KB = 1024 bytes = 2¹⁰ bytes
1 MB = 1024 KB = 2²⁰ bytes
1 GB = 1024 MB = 2³⁰ bytes

13.3 Word vs Byte Examples

Word size	Bytes per word
16-bit	2
32-bit	4
64-bit	8

Von Neumann vs Harvard

14.1 Von Neumann Architecture

Single shared memory for both program and data.
Single bus (typically) for memory access.
Components: ALU, CU, one memory space, I/O.
Cannot fetch instruction and data simultaneously on a single bus (von Neumann bottleneck).
Examples: 8085, 8086, 80386, 80486, most early PCs.

 ┌──────────┐
 │ CPU │
 └────┬─────┘
 │ one bus
 ┌────▼─────┐
 │ Program │
 │ + Data │ (same memory)
 └──────────┘

14.2 Harvard Architecture

Separate memories (and often separate buses) for program and data.

Allows simultaneous instruction fetch and data access.

Examples: ARM (many cores), AVR, PIC, SHARC, Sun SPARC (Harvard-style paths).

 ┌──────────┐ Program bus ┌─────────────┐
 │ CPU │───────────────────▶│ Program Mem │
 └────┬─────┘ └─────────────┘
 │ Data bus
 └──────────────────────────▶ Data Mem

14.3 Modified Harvard

Many modern chips use Harvard internally (split L1 caches) but von Neumann externally — exams may call this modified Harvard.

CISC vs RISC

Feature	CISC	RISC
Full name	Complex Instruction Set Computer	Reduced Instruction Set Computer
Instruction count	Large, variable format	Small, fixed format
Operand location	Often memory-to-memory	Register-to-register
Cycles per instruction	Often multiple	Often one
Control unit	Often microprogrammed	Hardwired, simpler
Examples	x86 (80386, 80486), VAX	ARM, AVR, PowerPC, MIPS
Memory access	Many instructions hit memory	MOV style loads/stores; ALU uses registers

15.1 CISC Characteristics (Detail)

One mnemonic may do much work (e.g. LDA with addressing modes).
Compiler can emit fewer instructions but each may be slower.
Microcode ROM inside CPU interprets complex opcodes.

15.2 RISC Characteristics (Detail)

Simple instructions execute quickly; pipelining is natural.
Highly pipelined superscalar RISC cores dominate mobile and server (ARM, RISC-V).
Memory access often limited to explicit load/store (LDA, STA, PUSH, POP on 8085 are CISC-style memory ops).

"RISC uses microprogrammed control" is usually false — that's CISC territory.