I/O Devices; Memory Unit; RAM Types

I/O Devices

Input devices bring programs and data into main memory under CPU control (keyboard, scanner, disk). Output devices present results (monitor, printer, disk).

The CPU issues I/O instructions or uses memory-mapped I/O / port-mapped I/O (detailed in microprocessor notes). I/O is slow compared to CPU speed; hence interrupts and DMA exist.

Class	Examples	Typical speed
Human input	Keyboard, mouse	Very slow
Human output	Display, printer	Slow–medium
Storage	Disk, SSD	Medium
Network	NIC	Variable

Memory Unit

A memory unit is a collection of storage cells plus circuits to transfer information in and out.

Two major classes:

RAM — Random Access Memory (read/write, volatile)
ROM — Read Only Memory (non-volatile, factory or field programmed)

Primary memory (main memory) is fast and directly addressable by the CPU (RAM). Secondary/auxiliary memory is larger and slower (disk, tape).

RAM is organized in partitions; each location has an address and contents (word or byte).

RAM Types

9.1 DRAM (Dynamic RAM)

Built from capacitor + transistor per bit.
Must be refreshed every 10–100 ms or data leaks away.
Slower, cheaper, higher density — used for main memory in PCs.

9.2 SRAM (Static RAM)

Uses a six-transistor latch per bit.
Retains data while power is on without refresh.
Faster, costlier — used for cache and on-chip memory.

9.3 NVRAM (Non-Volatile RAM)

Retains data when power is off (e.g. flash-backed RAM, battery-backed SRAM).
Used where persistence and speed both matter (firmware buffers, RAID cache).

Type	Volatile?	Refresh?	Speed	Cost	Typical use
DRAM	Yes	Yes	Medium	Low	Main RAM
SRAM	Yes	No	High	High	Cache L1/L2
NVRAM	No	Varies	Medium–High	High	Special systems

Input and Output Organization

An I/O interface connects a device with the processor bus and normally contains data, status and control registers. Programmed I/O makes the processor repeatedly test status and transfer each item. Interrupt-driven I/O lets the processor perform other work until the device requests service. Direct memory access transfers blocks between a device and main memory after the processor programs the controller.

Memory-mapped I/O assigns device registers ordinary addresses and uses normal load and store instructions. Isolated I/O uses a separate address space and special instructions. Input devices convert external information into digital data while output devices convert stored results into a usable external form. Device controllers absorb timing and protocol differences between fast processors and slower peripherals.

RAM Organization

Random-access memory permits any addressed location to be read or written without scanning preceding locations. SRAM stores each bit in a bistable circuit. It is fast and does not require refresh but uses more transistors per bit. DRAM stores charge in a capacitor. It provides higher density at lower cost but requires periodic refresh.

Memory capacity is the number of addressable locations multiplied by bits per location. Address lines select a location while data lines carry its word. Several chips can increase word width by operating in parallel or increase address capacity through chip-select decoding. Access time is the delay from a valid request to available data while cycle time is the minimum interval between complete operations.