Registers; ALU and Control Unit; System Buses

Registers

Registers are very fast storage locations inside the CPU. All data must pass through registers before the ALU can process it (in classical designs).

Register	Full Name	Function
MAR	Memory Address Register	Holds address of memory location to access
MDR	Memory Data Register	Holds data being transferred to/from memory
AC	Accumulator	Holds intermediate arithmetic/logic results
PC	Program Counter	Address of next instruction to fetch
CIR	Current Instruction Register	Holds instruction currently being executed

4.1 Data Flow During LOAD

PC → MAR (address of instruction)
Memory → MDR → CIR (instruction fetched)
Decode: operand address → MAR
Memory → MDR → AC (data loaded)

ALU and Control Unit

5.1 Arithmetic and Logic Unit (ALU)

The ALU performs:

Arithmetic: add, subtract, increment, decrement, sometimes multiply/divide

Logic: AND OR, NOT, XOR, compare

Operands typically come from registers (especially AC) and results return to AC or a general-purpose register.

5.2 Control Unit (CU)

The CU controls:

ALU operation selection
Memory read/write timing
I/O read/write
Bus signal assertion (RD, WR, etc. on real processors)

It provides timing and control signals so all components stay synchronized with the system clock.

Analogy: ALU is the "calculator"; CU is the "conductor" reading the score (instruction) and telling each section when to play.

System Buses

Buses are shared communication pathways connecting CPU, memory and I/O.

Bus	Width (typical)	Direction	Carries
Address	16–64 bits	Unidirectional (CPU → memory/I/O)	Memory addresses only
Data	8–64 bits	Bidirectional	Data and sometimes multiplexed address
Control	Few lines	Mixed	RD, WR, interrupt, clock, etc.

6.1 Address Bus

Carries addresses, not data.
Unidirectional: CPU (or DMA master) drives addresses outward.
Wider bus ⇒ larger directly addressable memory (e.g. 16 lines → 64 KB).

6.2 Data Bus

Carries operands, instructions, I/O data.
Bidirectional: read fills bus toward CPU; write drives bus from CPU.

6.3 Control Bus

Carries commands and status: memory read/write enable, interrupt acknowledge, bus grant, etc.

6.4 Block Diagram (Conceptual)

Keyboard ──┐
 ├──▶ [Data Bus] ◀──▶ CPU ◀──▶ [Address Bus] ──▶ RAM/ROM
Printer ──┘ ▲ │
 └── [Control Bus]
Timer ────────────────┘